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以下文章節錄自來源：
https://wccftech.com/amd-olympic-ridge-zen-6-ryzen-cpus
-get-integrated-npu-at-the-cost-of-igpu/
（https://reurl.cc/N2vANm）
https://x.com/Gotou_kai3/status/2066353017662886018


以下中文主要自Google翻譯，並略加潤飾。


Besides these, the platforms will also see some upgrades, such as more IO
capabilities, Wi-Fi 7 support, and optimized support for faster DDR5 memory
modules. As per the latest details, the upcoming AM5 boards will see support
for the full EXPO 1.2 feature stack, which includes DDR5 CUDIMM support along
with even better ULL profile kits.



The IO die on the AMD Ryzen "Zen 6" CPUs will also see some major changes. It
is said that AMD will be integrating an NPU within the IO die, which means
these will be the first standard AMD chips with an NPU. AMD does offer an NPU
on its AM5 desktop APUs, but these will be the first Non-APU designs with
such support.



At the same time, AMD is said to remove the onboard iGPU. Starting with AM5,
AMD featured a 2 CUs Radeon 710M iGPU on its desktop processors. This was
mostly used for business and offices, but could also be used for diagnostic
purposes. With the removal of this iGPU, those who want to diagnose
video-related issues, such as black screens or no displays when booting up,
will have to rely on a secondary dGPU (discrete GPU) if their primary one
isn't working as intended.



This won't be a major deal for desktop users, but it will surely limit the
diagnostic capabilities of the previous generation. Intel does offer its
desktop processors with iGPU-enabled and disabled variants. AMD will retain
iGPU capabilities across its APU lineup. Despite all of that, AMD's Olympic
Ridge line of Ryzen processors will be a disruptive desktop lineup, aiming
for enthusiasts and mainstream users in 2027, right in time to tackle Intel's
Nova Lake-S Desktop processors.



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為何AMD Zen6的IOD結構分配，會棄iGPU而全部轉移至NPU，
本人認為得從以下的幾個觀點來看：

(1)Windows 12的NPU硬性限制，與出爾反爾：

當初設計時（約2023～2024年）押注Windows 12＝Copilot+限制（NPU算力≧40TOPs），
但Micorsoft為保市占，有跡像可能下調NPU算力限制，恐再度事與願違。

(2)tsmc N3P產能緊缺、光罩成本上升、面積與良率問題：

tsmc N3P高貴又缺乏，為保證產量與出貨，合併桌機IOD、筆電APU與顯卡到N3P製程，
為提升良率和單片晶圓產品數而縮減設計面積。

(3)封裝升級造成的量能爭搶，與NPU/GPU多Die封裝衍生諸多不確定性：

封裝升級（2.5D互連封裝技術）造成成本上升，
且多Die封裝面臨應力平衡問題，也需防止專利抵觸（例如Intel空矽片設計）、
以及NPU的微軟認證進度挑戰（接受獨立NPU封裝設計）等。

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※ 作者: uodam64402 2026-06-17 01:16:02
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